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Embedded Systems Conference Coverage
Most Popular / Embedded
Submitted By utahsaint365 382 days ago
Don't expect the same old stuff at the 2007 Embedded Systems Conference, scheduled for April 1-5 at the McEnery Convention Center in San Jose, Calif. This year's show will be virtually bursting at the seams, with many vendors setting up shop outside the main exhibit hall. Vendors seem to be cautiously optimistic, now that issues like the European Union's Restrictions on Hazardous Substances (RoHS) are being addressed and the latest standards-based technologies like Serial ATA (SATA) and PCI Express are commonplace. In fact, this optimism has triggered the return of numerous exhibitors and attracted a host of new vendors.
Tags: embedded esc
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Cadence Collaborates With IBM, Samsung and Chartered to Deliver 65-NM Reference Flow
Most Popular / EDA
Submitted By utahsaint365 382 days ago
Cadence announced immediate availability of the 65-nanometer Common Power Format (CPF) enabled reference flow targeting the Common Platform technology. This reference flow is the next step in the ongoing collaboration between Cadence and the Common Platform coalition comprised of IBM, Chartered Semiconductor Manufacturing and Samsung. Cadence worked closely with the Common Platform technology partners to develop this 65-nanometer flow. It is based on the Cadence digital IC design platform including Encounter Timing System and CPF to accelerate time to market for low-power system-on-chip (SoC) designs.
Tags: 65-NM cadence Wafer
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Samsung Electronics Develops New, Highly Efficient Stacking Process for DRAM
Most Popular / Embedded
Submitted By utahsaint365 382 days ago
Samsung has developed the first all-DRAM stacked memory package using 'through silicon via' (TSV) technology, which will soon result in memory packages that are faster, smaller and consume less power. The new wafer-level-processed stacked package (WSP) consists of four 512 megabit (Mb) DDR2 (second generation, double data rate) DRAM (dynamic random access memory) chips that offer a combined 2 gigabits (Gb) of high density memory. Using the TSV-processed 2Gb DRAMs, Samsung can create a 4 GB (gigabyte) DIMM (dual in-line memory module) based on advanced WSP technology for the first time. Samsung's proprietary WSP technology not only reduces the overall package size, but also permits the chips to operate faster and use less power.
Tags: ddr2 samsung wafer
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